The present invention relates generally to serial data transmission, and, more specifically, to the recovery of a clock signal and data bits from a serial data bit stream at an asynchronous serial interface receiver.
Recently, there has been a consistent rise in the use of the serial data transmission technology in digital data transmission. Several industries are undergoing a transition from parallel to high-speed serial interfaces to reduce system costs, simplify system design, and provide scalability to provide higher bandwidths. An important advantage that serial interfaces provide is lower pin counts per connection. As a result, more input/output (I/O) channels can be implemented on one integrated circuit (IC) chip as compared to parallel data transmission. This reduces the cost per I/O channel in an IC. Serial data transmission also allows fabrication of smaller IC packages having fewer ICs, less traces, and smaller board area and/or PCB layers. Recently, serial data transmission has become capable of delivering data transmission speeds in the range of 2-10 Gbps. Additionally, serial interfaces provide higher clock rates than other interfaces due to the use of asynchronous data transfer with embedded clock, full duplex point-to-point connection and some technological advances in the Physical Layer (PHY) signaling such as low-voltage differential signaling, 8 b/10 b encoding and pre-emphasis (signal equalization).
Several emerging data transmission standards, such as MPHY by Mobile Industry Processor Interface (MIPI), Serial AT Attachment (SATA), Universal Serial Bus (USB) 3.0, Peripheral Component Interconnect (PCI) Express, 1 GB and 10 GB Ethernet, RapidIO, and Fiber Channel, have serial data transmission as their core technology. These interfaces are widely used in various market segments such as in all facets of telecommunications, optical transceivers, data and storage networks, wireless products, and computing systems in general.
A serial data transmission system transmits data bits sequentially over a transmission channel. Generally, a serial data transmission system includes a transmitter module, a receiver module, and a transmission channel. The transmitter module transmits data serially over the transmission channel without an accompanying clock signal. The receiver module receives the serial data stream, recovers the serially transmitted data from the received serial data stream, and performs a serial-to-parallel conversion. The serial-to-parallel conversion results in parallel data streams that enable the receiver module to operate at lower frequencies than the serial data rate. The transmitter and receiver modules may be part of a wide area network or implemented as integrated circuits located on a single circuit board or on two different circuit boards or two IP blocks within the same chip. The transmission channel may be a communication satellite link, a fiber optic cable, back plane connectivity, chip-to-chip interconnection or connectivity inside a chip.
During serial data transmission, the transmitter module converts the parallel data into serial data by time-division multiplexing the data bits. Each data bit sent over the transmission channel is represented as a pulse of a predetermined time period of a high or low voltage level. The switching between the high and low voltage levels occurs in synchronization with a clock signal local to the transmitter module. However, due to scarcity of resources, the clock signal is not transmitted to the receiver module. Thus, in order to recover data from the serial data stream, the receiver module detects bit boundaries using clock and data recovery schemes such as phase adjustment (phase alignment) and phase picking.
In the phase adjustment scheme, a phase locked loop (PLL) is used to adjust the sampling instant to the signal eye center of the received signal. This method of data recovery entails the usage of a digital phase detector, which calculates a phase angle between an input signal and the clock signal. As digital phase detectors are edge sensitive circuits and the received input signal is distorted due to interference with various unavoidable effects in the transmission channel, the digital phase detectors may lead to incorrect calculation of the phase angle, which is a disadvantage of the phase adjustment scheme. The occurrence of the above-mentioned inaccuracy may be suppressed with an inert control system. An inert control system prevents immediate unlocking of the PLL. However, incorrect calculation of the phase angle leads to a reduction in the jitter budget even when using an inert control system. Thus, for the same BER (Bit Error Rate), the received data signal needs to have a larger signal eye opening when using a PLL based phase adjustment (phase alignment) clock and data recovery scheme.
In the phase picking scheme, the serial data stream is sampled at a frequency higher than the frequency of the transmitter module clock signal. Alternatively, the sampling is done using multiple phases of a reference clock signal local to the receiver module. The multiple phases are obtained by phase shifting the reference clock signal by a phase angle that depends upon a predefined count of multiple phases to be obtained. The sampling of the data stream generates a plurality of data samples corresponding to one clock cycle width of the reference clock signal at the receiver module. Thereafter, the data samples corresponding to a phase of the reference clock signal that represents the transmitted data bits more correctly as compared to other phases are selected. The data samples are selected based on an assumption that the data bits span for equal time periods and that each data bit spans for an equal count of phases of the reference clock signal. If an eye diagram is plotted of an ideal data stream, bit transitions will lie at a particular phase of the reference clock signal. On the other hand, if there is jitter in the received data stream or sampling phases of the reference clock signal, the bit transitions will be spread around a particular phase of the reference clock signal. The shorter the bit transition spread, the better the existing methods work for calculating the phase for sampling the received data stream, thereby resulting in low bit error rate (BER).
However, in actuality due to the non-ideal nature of the transmitter module and the transmission channels, some received data bits may become prolonged and some data bits may become shortened as compared to the ideal bit width. As the speeds of serial interfaces increase, the ratio of bit width of prolonged bits and shortened bits increases. For serial interfaces that work at high speed, a shortened bit can become less than 50% of its ideal width and an elongated bit can become more than 150% of its ideal width. This effect can cause a spread of distribution of bit transitions of the received data bit stream throughout the eye opening, resulting in a very narrow eye opening or an almost closed eye. Existing methods for clock and data recovery fail in such cases of widely distributed bit transitions. This shortcoming will be explained in more detail below with reference to FIG. 2B.
Many of the above stated shortcomings of the conventional phase alignment scheme are overcome by the phase picking scheme. Since the stability constraints are absent, the phase picking scheme achieves a very high bandwidth. However, the phase picking decision is prone to latency due to the involvement of lengthy calculations.
FIG. 1 is a timing diagram 100 illustrating generation of multiple phases for an 8× oversampling scheme. The timing diagram 100 includes a reference clock signal 102, and phase signals 104a, 104b, 104c, and 104d. The phase signals 104a, 104b, 104c, and 104d correspond to phase 0 (ph0), phase 1 (ph1), phase 3 (ph3) and phase 7 (ph7) respectively. Phases 2, 4, 5, and 6 are not shown for simplicity and clarity.
The reference clock signal 102 is provided to a multiple-clock generation unit that generates the phase signals 104a, 104b, 104c, and 104d from the reference clock signal 102. When the count of phases generated is 8, each of the multiple phases is shifted from one another by 360°/8=45°. Similarly, mutual phase angles between different phase signals may be calculated for different counts of phases to be generated.
Referring now to FIG. 2A, a timing diagram 200a depicting sampling of an input bit stream is shown. The timing diagram 200a includes the waveforms corresponding to an input bit stream 202a. The input bit stream 202a is pre-encoded by a transmitter using the 8 b/10 b encoding scheme or any other encoding scheme that ensures a minimum and sufficient number of transitions in the input bit stream 202a. The input bit stream 202a includes a waveform 204a and a waveform 204b. The timing diagram 200a further includes accumulated phase transitions 206a, and phases 208a, 208b, 208c, 208d, 208e, 208f, 208g, and 208h corresponding to phases 0-7 of the reference clock signal 102 (FIG. 1) respectively.
The input bit stream 202a includes received data bits Rbit0, Rbit1 Rbit2, and so on. It may be observed that the received data bits Rbit0-Rbit9 have equal bit widths. Therefore, all the received data bits span an equal number phases i.e., 8. For example, the waveform 204a that corresponds to received data bit Rbit2, spans 8 phases. It may be further observed that all the bit transitions occur at phase 208a. Therefore, phase 208a is the transition phase.
Referring now to FIG. 2B, a timing diagram 200b depicting sampling of an input bit stream 202b is shown. The timing diagram 200b includes the waveforms corresponding to the input bit stream 202b. The timing diagram 200b also includes a waveform 204c, a waveform 204d, a waveform 204e, and accumulated phase transitions 206b. 
The input bit stream 202b includes received data bits such as Rbit0, Rbit1, Rbit2, and so on and is similar to the input bit stream 202a of FIG. 2A. The input bit stream 202b is sampled using the phases of the reference clock signal 102 (FIG. 1) such as phases 208a-208h to obtain multiple data samples of each data bit in the input bit stream 202b. The received data bit Rbit5 corresponding to the waveform 204d is a shortened bit since it spans only 2 phases, i.e., the phases 208b and 208c. Further, the received data bit Rbit6 corresponding to the waveform 204e is an elongated bit since it spans eleven phases. Additionally, it may be observed that the received data bit Rbit2 corresponding to the waveform 204c is of normal length since it spans 8 phases.
The obtained data samples are stored in a memory for further processing. Subsequent to the data sample collection, an average transition phase is calculated based on the transitions between two consecutive phases. The average transition phase represents a phase corresponding to one in which the number of bit transitions is highest or the probability of occurrence of bit transitions is highest. Thereafter, a final center phase is identified by adding a fixed offset or a statistically calculated offset to the average transition phase. The fixed offset is added such that the final center phase obtained has the least probability of occurrence of bit transitioning as it is farthest from the average transition phase. Subsequently, the data samples corresponding to the final center phase are extracted. For example, in FIG. 2A it may be observed that phase 208a i.e., ph0 is the phase in which all bit transitions happen. Hence phase 208a may be identified as the average transition phase. Thereafter, an offset of four phases may be added to phase 208a to identify phase 208e (phase 0+4=phase 4) as the final center phase. Then, the data samples corresponding to phase 208e are extracted.
In an example from FIG. 2B, the accumulated phase transitions 206b shows that there are bit transitions at phases 208a, 208d, 208g and 208h. Like the example shown in FIG. 2A, if phase 208a is identified as the average transition phase using the most transitioning phase criterion and an offset of four phases is added, then phase 208e is identified as the final center phase. As can be seen from the timing diagram 200b, if phase 208e is identified as the final center phase, the received data bit corresponding to the waveform 204d is skipped as it is a shortened data bit. Instead, the value of the received data bit corresponding to the waveform 204e is extracted twice. Such erroneous final center phase estimation leads to a high BER. Additionally, subsequent to the addition of offset to the average center phase transition, the final center phase thus obtained may be one of the transition phases. For example, if phase 3 (phase 208d) is selected as an average transition phase, then the final center phase is calculated by adding an offset of 4 phases to phase 3 to obtain phase 7 (phase 208h) as the final center phase. FIG. 2B shows that phase 7 is a transitioning phase. This will further increase the BER. However, high speed serial interfaces, such as MIPI-MPHY, USB 3.0, SATA, and PCI Express, have very low BER (10^-12) requirements.
Further, the accumulated phase transitions 206b show that phases 208b and 208c, and phases 208e and 208f do not include a transition in any of the waveforms that represent the received data bits. Therefore, the final center phase is selected from either the phases 208b and 208c or the phases 208e and 208f. If either of phases 208b or 208c is selected as the final center phase, the values of the received data bits corresponding to the waveforms 204c, 204d, and 204e are obtained correctly.
Additionally, defects, such as clock jitter, band limitation of the communication channels, and Inter Symbol Interference (ISI), may reduce the effective usable eye opening to almost 0 percent and distribute the bit transitions throughout the eye. This may further result in the failure of the existing statistical clock and data recovery methods. Accordingly, it would be advantageous to be able to recover a clock signal and data bits from a serial bit stream reliably and with a low BER.